1. Field of the Invention
The present invention relates to a method for forming contact openings to selected locations of the surface of a MOS integrated circuit.
2. Discussion of the Related Art
For MOS integrated circuits in which the primary structures are of very small dimensions, for example, in which the gate structures have a length smaller than one tenth of a micrometer, one of the limitations to miniaturization is the forming of contact openings to semiconductor areas of the structure. This will be illustrated in relation with FIG. 1.
The left-hand portion of FIG. 1 illustrates an example of a MOS transistor formed in an active area of a substrate 1 delimited by shallow trenches 2 filled with an insulator (STI). This MOS transistor comprises an insulated gate 3 formed on a thin gate insulator layer 4. Gate 3 is conventionally made of polysilicon and gate insulator 4 is silicon oxide, although there currently is a tendency to preferring other insulators with a smaller dielectric constant. This gate is used to delimit a first implanted area 5 in the active area of substrate 1. Then, the gate is surrounded with spacers, for example, as shown, with silicon nitride spacers 7 having an L-shaped cross-section and separated from the gate and from the substrate by a very thin oxide layer. The spacers are used to delimit more heavily-doped source and drain regions 8 and 9 in substrate 1. Preferably, the upper surface of gate 3 and the upper surfaces of source and drain regions 8 and 9 are formed of a layer of a metal silicide to improve the conduction and favor the contact making. Metal silicide areas are indicated in FIG. 1 and in the following drawings by a thick line with no reference numeral.
In the right-hand portion of FIG. 1, two transistors analogous to that of the left-hand portion, arranged side by side without being separated by an insulating area, have been shown. The two adjacent transistors have a common drain/source region 11 on which a contact may be desired to be formed.
A structure in which the gate lengths are of 0.65 nanometer, the widths of lightly-doped areas 5 under spacers 7 are on the order of 60 nm, and the more heavily-doped areas covered with oxide 8, 9, 11 have a width on the order of from 30 to 60 nm, the height of gate 3 above the substrate surface being for example 150 nm, will for example be considered.
A conventional method for forming a contact opening is illustrated in FIG. 2. The entire structure illustrated in FIG. 1 is covered with a protective layer 20, for example, a silicon nitride layer. An insulating layer 21, re-etched by chem-mech etch to have a planar upper surface, is then deposited. Layer 21 is covered with a mask 22. It should be noted that this insulating layer remains in place at the end of the process and must be of fine quality. It results, for example, from a high-density plasma deposition.
Assume that a first contact with a drain/source region 8 close to an insulating region 2 and a second contact with a drain/source region 11 arranged between two adjacent transistors are desired to be established. For this purpose, openings 23 and 24 are formed in mask 22 above the regions which are desired to be reached and insulating layer 21, followed by protection layer 20, is etched to release the contact areas. The function of protection layer 20 is well known per se. This protection layer is used as an etch stop for layer 21 especially to avoid overetching the insulation forming insulating regions 2 between transistors and creating defective regions at the limits of this insulator.
The opening of the first contact to drain/source region 8 poses no critical problem since it is possible to overflow with no inconvenience above insulating layer 2.
However, the opening of the second contact to drain/source region 11 intermediate between two adjacent transistors poses critical problems given the involved dimensions. Indeed, the accuracy of the positioning of mask 22 with respect to the previously-formed layers is on the order of 80 nm. This difference is smaller, in the context of the above-described example, than the distance between region 11 and the tops of the adjacent gates 3. Thus, in case of an excessive shifting of opening 24 of the mask, the silicon nitride above region 11 and above one of the adjacent gates 3 will have to be etched at the same time, which results in a risk of short-circuit after metallization. This compels to increasing the transistor dimensions in order to solve this problem of contact opening forming accuracy.
Although only two types of contact openings have been described hereabove, it should be noted that other opening types will generally be provided, for example, openings enabling directly making contacts on the upper silicided layers of gates 3. These openings generally do not pose very critical problems, conversely to the establishing of contacts towards intermediary regions between neighboring gates.